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Student's Guide to VHDL
A guide to VHDL for digital system modeling. It aims to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification.
455,00 DH
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A guide to VHDL for digital system modeling. It aims to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification.
| ISBN / EAN | 9781558608658 |
|---|---|
| Auteur | Ashenden, Peter J. (Adjunct Associate Professor, School of Computer Science, University of Adelaide, Australia) |
| Editeur | Elsevier Science & Technology |