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Verification Techniques for System-Level Design
Explains how to verify SoC logic designs using 'formal' and 'semi-formal' verification techniques. This book covers various aspects of high-level formal and semi-formal verification techniques for system level designs.
820,00 DH
Sur commande
Explains how to verify SoC logic designs using 'formal' and 'semi-formal' verification techniques. This book covers various aspects of high-level formal and semi-formal verification techniques for system level designs.
| ISBN / EAN | 9780123706164 |
|---|---|
| Auteur | Fujita, Masahiro (Professor, VLSI Design & Education Center, University of Tokyo, Japan.) |
| Editeur | Elsevier Science & Technology |